1. Field of the Invention
The present invention relates in general to the field of computer circuitry. More specifically, embodiments of the invention are systems and methods for measuring a clock duty cycle without using a reference clock for calibration.
2. Description of the Related Art
The duty-cycle of a high-speed clock is a very important aspect of modern integrated circuits, such as high-performance microprocessors. For example, either the positive or the negative cycle of a clock can be used for memory access and the memory access speed is directly related to the duration of the clock pulse and thus the duty cycle. In theory, a fifty percent duty cycle clock is preferred from a phase-locked loop (PLL) and the clock distribution circuitry. However, the optimum duty cycle of a clock for maximum system performance will vary from one circuit to another due to process variation and model-to-hardware correlation.
In general it is difficult to measure the duty cycle of a clock, since any logic that is used to extract the duty cycle of a clock will also lead to duty cycle degradation of the original clock. In addition, most prior techniques for measuring the duty cycle of a clock require an off-chip reference clock for calibration.
To help optimize design, it is preferable to calculate the duty cycle of a clock using on-chip hardware. A clock duty cycle is sensitive to many different factors, including operating frequency, operating temperature, supply voltage, circuit design style, circuit loading, and process (e.g., variations in the doping, threshold voltage, mobility, gate oxide thickness, etc. across single and/or multiple wafers). Because so many different factors may affect duty cycle, it is important to be able to accurately measure clock duty cycle at the point of use on the chip under actual operating conditions.
It is apparent, therefore, that there is a need for an improved system and method for measuring the duty cycle of a clock using on-chip hardware without a reference clock.